Exemplary embodiments relate to a semiconductor memory device and a method of operating the same.
As semiconductor technology advances, the operating speed of a semiconductor memory device increases and power consumption thereof decreases.
In increasing the data I/O rate of the semiconductor memory device, data is outputted in synchronism with a reference clock signal and, particularly, with both the rising edge and the falling edge of a clock signal.
In obtaining appropriate system performance, the semiconductor memory device may be designed to output or receive 16, 32, or 64 data at one step. In order to output the plurality of data at one step, appropriate data lines and related circuits (e.g., data output buffers) corresponding to the respective output data amount are to be included in the semiconductor memory device.
If the number of data lines is increased in order to output a large amount of data at one step, the area of the semiconductor memory device may increase. Accordingly, an increase in the number of data lines is to be limited.